搜索资源列表
hex7segb
- Implimentation of the switches and 7 segment display bit counter on an Altera DE2 baord via VHDL code on the Cyclone II FPGA
TLC1620
- 基于FPGA的Verilog语言实现的六十进制计数器-FPGA-based Verilog language implementation of six decimal counter
FPGAbasedprogramable-PROWER
- 本设计提出了一个基于FPGA的程控稳压电源的方案。通过按键向FPGA输入信号，FPGA得到“十位”和“各位”计数脉冲信号，通过计数器模块计数，内部计数器的信号一路送给外部显示电路来显示当前的电压值，另一路经过D/A转换器（DAC0832）输出模拟量，再经过运算放大器隔离放大，控制输出功率管的基极，随着功率管基极电压的变化而输出不同的电压，同时实现双路输出。实际测试结果表明，本系统具有易调节，高可靠性，操作方便，电压稳定度高，其输出电压采用了数字显示的特点。-This design present
Alarm
- The aim this project is to implement the functionality of a digital alarm clock on a FPGA. As soon as the FPGA is switched on, the clock starts. The alarm can be set using the dip-switches provided on the FPGA board. This is indicated through the LED
SyncounterFinal
- 在Xillinx ISE 平台上利用VHDL语言实现同步计数器，利用状态机实现，导入FPGA版点亮7段数码管并实现加、减计数功能。-The programme realizes a counter based on synchronous state machines, and it can be download to a FPGA chip.
cepincexiang
- 基于FPGA的频率计，能在数码管上显示频率 相位等信息，-FPGA-based frequency counter, frequency and phase information can be displayed on the LED,
FPGA__source-code__Verilog
- FPGA部分基础功能源代码，适合初学者进行学习仿真，代码可读性强，通俗易懂，逻辑清晰。包括触发器，全加器，分频，并串转换，计数器，序列发生器等Verilog语言源代码。- Part of the basic functions of the source code for FPGA.Suitable for beginners to learn the simulation, the code readable, easy to understand, clear logic. Includ
axi-timer
- 这是Xilinx AXI定时器的说明手册，对于进行FPGA开发的工程师有参考价值 -The LogiCORE IP AXI Timer/Counter is a 32/ 64-bit timer module that interfaces to the AXI4-Lite interface.
fp
- FPGA基础程序，分频器的设计及实现，利用计数器实现-FPGA based program, crossover design and implementation, realized by the counter
01_Counter_Design
- 基于FPGA控制的4位计数器，已经过调试仿真验证，可用-FPGA-based control of the 4-bit counter, has been debugging simulation available
shiyan2
- Verilog HDL实现十进制计数器,FPGA ISE开发环境- Verilog HDL decimal counter
ledbuff
- fpga单片机通过数码管实现1S自加功能，时间通过计数器实现-The fpga single chip machine implements the 1S self-addition function through the digital tube, and the time is achieved through the counter
vhdl
- 10秒计数器模块ＶＨＤＬ源程序，在FPGA中实现计数器功能(10 seconds counter module VHDL source code, in FPGA realize counter function)
Johnson_counter
- 利用 fpga 实现约翰逊计数器的功能(fpga Realize the function of Johnson counter)
shi01
- FPGA上机文件一所以在FPGA中采用同 步设计非常重要 MAX+PLUS II可以计算出数据传输需要(fpga Several of the largest chip operating frequency I would be grateful if the output value of counter FFFFC- FE0FF simulation waveform between the print out (only EPF10K70RC240-4 chips, the maximu
wb_counter-1.0.1.tar
- wishbone counter for fpga
04_led_test
- FPGA入门实验，简单的流水灯，计数器的使用较规范(FPGA introductory experiment, simple flow lamp, the use of counter is more standard)
dif
- FPGA设计中，实现基准时钟的分频模块，该模块是将外围电路中所提供的50MHZ将其分频，对时钟模块作用后产生一秒一秒的时钟信号，另外对显示模块的计数器提供时钟实现显示模块的扫描功能。(The design of FPGA, the reference clock frequency module, this module is provided in the peripheral circuit of the 50MHZ frequency, the clock module generates
at7_ex03
- 使用FPGA内部的PLL产生时钟，计数器循环计数驱动LED闪烁。基于vivado平台编写的Verilog代码(Use FPGA's internal PLL to generate clock, counter cycle counting drive LED flicker. Verilog code based on vivado platform)
jishuqi
- FPGA应用底层开发的逻辑单元slice连线实现计数器的功能，包含代码及仿真(FPGA applies the logic unit slice connection that is developed at the bottom to realize the function of counter, including code and simulation.)